The invention relates to a semiconductor device with a transistor of the lateral DMOS type, comprising a semiconductor body having a semiconductor substrate of a first conductivity type and, provided on the substrate, an epitaxial semiconductor layer bordering on a surface of the semiconductor body, said semiconductor body being provided, at the interface between the epitaxial layer and the substrate, with a layered region of the first conductivity type and a buried layer of a second, opposite, conductivity type, which extends between the layered region and the substrate and electrically insulates them from each other, at least three, mutually separated backgate regions of the first conductivity type, which border on the surface and are each provided with a source region of the second conductivity type, and a number of drain zones in the form of heavily doped surface regions of the second conductivity type, situated between the backgate regions and separated from said backgate regions by intermediate slightly doped drain extensions of the second conductivity type, being formed in a part of the expitaxial layer, situated between the buried layer and the surface.
Such a device is known, inter alia, from the patent document U.S. Pat. No. 5,146,298.
Transistors of the lateral DMOS type, often referred to as LDMOST, are frequently used as a switch in power circuits for turning on and off large currents. A known circuit is, for example, a (half) bridge circuit by means of which an electric current can be sent through a load in two directions. In this circuit, two transistors, customarily of the n-channel type, are arranged in series between a high voltage and a low voltage, whereby the source of the one transistor, hereinafter referred to as low side transistor or LS transistor, is connected to the low voltage and the drain of the other transistor, hereinafter referred to as high side transistor or HS transistor, is connected to the high voltage, and the drain of the LS transistor and the source of the HS transistor are both connected to the load via the output. The gates of the transistors are connected to a control circuit by means of which the transistors can be alternately turned on and off, that is if one transistor is in the "on" state, the other transistor is in the "off" state. In these and other applications, the transistor is often subjected to an inductive load. As a result, if a transistor changes from the conducting "on" state to the non-conducting "off" state, it is possible, for example, in the case of the above-described bridge circuit, that the voltage on the output becomes higher than the high supply voltage or lower than the low supply voltage. Due to this, in embodiments where the drain of the LS transistor forms a pn-junction with the substrate, this pn-junction may become forward poled during operation and hence inject electrons into the substrate. This injection of minority charge carriers into the substrate can be precluded, or at least reduced substantially, in an LDMOST of the type described in the opening paragraph in which the drain of the LS transistor does not form a pn-junction with the substrate but, instead, with said p-type layered region which is electrically insulated by the n-type buried layer from the p-type substrate.
FIG. 4 of the above-mentioned patent U.S. Pat. No. 5,146,298 shows a structure with an n-type epi layer on a p-type substrate and a double buried layer, said layered region of the first conductivity type, which, in the example, is the p-type, is formed by a second buried layer which is electrically insulated from the substrate by the n-type buried layer. The p-type buried layer isolates the n-type buried layer from an island-shaped part of the n-type epitaxial layer in which the transistor is formed. The island is delimited by deep p-type insulation regions which are connected to the p-type buried layer and form an electrical connection of the buried layer. If, during operation, the voltage on the drain becomes lower than the low supply voltage, the pn-junction between the drain and the p-type buried layer may become forward poled instead of the pn-junction from the drain to the substrate, thus precluding injection into the substrate.
In practice it has however been found that in such a configuration new drawbacks may occur, in particular as the size of the transistor increases in connection with the current to be dealt with. For example, if there is a high positive voltage on the drain, it is possible that a vertical npn action occurs in which the drain serves as the collector, the buried p-type layer as the base and the buried n-type layer as the emitter. Such an npn action may also occur under dynamic conditions in the case of a large dV/dt on the drain. It is an object of the invention to provide, inter alia, a lateral DMOS transistor in which, apart from injection of minority carriers into the substrate, also npn action between the drain and the buried n-type layer is precluded. To achieve this, a semiconductor device of the type described in the opening paragraph is characterized in that the back-gate regions are each conductively connected to said layered region of the first conductivity type by means of a zone of the first conductivity type.